The present invention relates to a semiconductor device, in particular a semiconductor device including a clock-and-data recovery circuit that extracts data from an externally-supplied input signal and an oscillator circuit that generates a clock signal to be supplied to the clock-and-data recovery circuit.
In recent years, the communication speed between semiconductor devices has been improving. As for the communication method, a parallel data transfer method and a serial data transfer method have been used. However, in recent years, it is believed that the serial data transfer method is superior to the parallel data transfer method in terms of its ability to increase the data transfer rate. Therefore, the serial data transfer method has been used more widely.
In the serial data transfer method, data signals are modulated by using a transmission clock and transferred as serial data. Then, a receiver circuit extracts the sampling clock and the data signals from the serial data. A clock-and-data recovery circuit is used for the extraction of the sampling clock and the data signals.
Further, it is essential to generate a highly-accurate clock as a transmission clock in the serial data transfer method. In general, this highly-accurate clock is generated by using a quartz resonator. However, quartz resonators are very expensive. Therefore, it has been one of the causes of high system costs. Accordingly, Japanese Unexamined Patent Application Publication No. 2007-135189 discloses a technique to generate a highly-accurate transmission clock by using a resonator having a lower accuracy than that of the quartz resonator. Further, Published Japanese Translation of PCT International Publication for Patent Application, No. 2008-535387 discloses a technique to control the frequency of a clock signal that is generated on the receiver side based on information obtained from a received signal, though its purpose is not to generate the transmission clock. The technique disclosed in Japanese Unexamined Patent Application Publication No. 2007-135189 is explained hereinafter.
Firstly, FIG. 7 shows a block diagram of a communication system 100 disclosed in Japanese Unexamined Patent Application Publication No. 2007-135189. As shown in FIG. 7, the communication system 100 includes a device 101 and a host 102. The device 101 and the host 102 include their respective transmitting/receiving circuits. In FIG. 7, only the transmitting/receiving circuit of the device 101 is illustrated. The device 101 receives a signal RX from the host 102. Further, the device 101 transmits a signal TX to the host 102. The host 102 generates a reference clock by using a reference signal generation source 120, which is formed from a quartz resonator or the like, and operates based on this reference clock. Meanwhile, the device 101 generates a reference clock by using a reference signal generation source 103, which is formed from a ceramic resonator, and operates based on this reference clock.
Note that the device 101 includes a synchronization establishment unit 111, a frequency error detector 112, a frequency generator 113, and a serializer 114. The synchronization establishment unit 111 receives a signal RX, which is received by the device 101, and extracts a clock and data from the signal RX. Then, the synchronization establishment unit 111 outputs the extracted clock as a reception signal RS and outputs the extracted data as a synchronization establishment signal SCS. Further, the synchronization establishment unit 111 converts the data into a parallel signal according to the clock, and outputs the parallel signal as reception data DT. The frequency error detector 112 receives the reception signal RS, the synchronization establishment signal SCS, a reference clock Fref, and a transmission signal TS. Then, the frequency error detector 112 detects a frequency difference between the reception signal RS and the transmission signal TS and thereby outputs a frequency adjustment signal FCS. The frequency generator 113 outputs the transmission signal TS whose frequency is determined based on the frequency adjustment signal FCS and the reference clock Fref. The serializer 114 receives the transmission signal TS and transmission data DR, and outputs a signal TX.
Note that the reception signal RS, which is extracted from the signal RX by the device 101, has the same frequency as that of the highly-accurate clock generated in the host 102. In the device 101, the transmission signal TS is generated based on this reception signal RS. That is, it is possible to generate a highly-accurate clock by using a resonator having a low accuracy in the device 101.